Continued scaling of complementary metal oxide semiconductor (CMOS) technology is reaching physical limits in device performance. For example, parasitic resistances and capacitances are becoming a fundamental limiting factor to improvement of device performance at reduced technology nodes. New materials and device architectures are thus required in order to overcome these fundamental scaling obstacles that degrade device performance.
One approach to overcome these limiting effects is to increase the drive current of the metal-oxide-semiconductor field effect transistor (MOSFET) or MOS transistor device by increasing the mobility of the carriers in the channel. It is well known that the application of mechanical stress on channel regions can substantially improve or degrade the mobility of electrons and holes in a semiconductor; however, it is also known that electrons and holes respond differently to the same type of stress. For example, the application of compressive stress in the longitudinal direction of current flow is beneficial for hole mobility, but detrimental for electron mobility. The application of tensile stress in the longitudinal direction is beneficial for electrons, but detrimental for holes.
State of the art technology has used stressed nitride liners that are deposited after silicidation to apply longitudinal stress to the channel and therefore increase the current drive of CMOS devices. However, it is imperative to develop an integration scheme that allows the desired application of stress (compressive or tensile) on appropriate areas of devices (NMOS transistor devices or PMOS transistor devices) to maximize performance of CMOS technology.
Accordingly, it is desirable to provide integrated circuits with improved performance and methods for fabricating integrated circuits with improved performance through selectively stressing channel regions and selectively stressing body contacts. Also, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with longitudinally stressed channel regions and laterally stressed body contacts. Further, it is desirable to provide integrated circuits and methods for fabricating integrated circuits in which PMOS transistor devices are formed with compressive stress in the longitudinal direction and with tensile stress in the lateral direction. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.